Download A Systolic Array Optimizing Compiler by Monica S. Lam PDF

By Monica S. Lam

This publication is a revision of my Ph. D. thesis dissertation submitted to Carnegie Mellon collage in 1987. It files the learn and result of the compiler expertise constructed for the Warp desktop. Warp is a systolic array equipped out of customized, high-performance processors, each one of that can execute as much as 10 million floating-point operations consistent with moment (10 MFLOPS). less than the path of H. T. Kung, the Warp computer matured from a tutorial, experimental prototype to a advertisement made of basic electrical. The Warp desktop confirmed that the scalable structure of high-peiformance, programmable systolic arrays represents a realistic, cost effective solu­ tion to the current and destiny computation-intensive functions. The luck of Warp ended in the follow-on iWarp venture, a joint venture with Intel, to strengthen a single-chip 20 MFLOPS processor. the provision of the hugely built-in iWarp processor could have an important influence on parallel computing. one of many significant demanding situations within the improvement of Warp was once to construct an optimizing compiler for the laptop. First, the processors within the xx A Systolic Array Optimizing Compiler array cooperate at a good granularity of parallelism, interplay among processors has to be thought of within the iteration of code for person processors. moment, the person processors themselves derive their functionality from a VLIW (Very lengthy guideline notice) guide set and a excessive measure of inner pipelining and parallelism. The compiler includes optimizations relating the array point of parallelism, in addition to optimizations for the person VLIW processors.

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2. Programmability of synchronous models Consider the following example. Suppose we want to evaluate the polynomial P(x)=C~+Cm-Ixm-I+ ... +Co for Xl' ••. ,XII' By Homer's rule, the polynomial can be refonnulated from a sum of powers into an alternating sequence of multiplications and additions: P(x)=«CmX+Cm-l)x+ ... +C1)x+Co The computation can be partitioned using either the parallel or pipelined model. To evaluate the polynomials according to the parallel model, each cell in the array computes P(x) for different values of x.

This chapter presents the architecture of the lO-cell prototype system in detail, as this is the architecture on which the research is based. Major revisions to the prototype in designing the PC machine are also described. This chapter also discusses the application domain of the Warp architecture, as well as its programming complexity. 1. The architecture Warp is integrated into a general purpose host as an attached processor. There are three major components in the system-the Warp processor array (Warp array), the interface unit (1U), and the host, as depicted in Figure 2-1.

For example, Leiserson and Saxe's retiming lemma gives the user the illusion that broadcasting is possible [41]. It converts all broadcasting signals to local propagation of signals. The cut theorem introduced by Kung and myself transfonns systolic designs containing cells executing operations in single clock cycles to arrays with pipelined processors [36]. 2. A limitation common to both tools is that they are designed for algorithms whose communication pattern is constant across time. A programmable array of powerful cells is capable of a far more general class of problems than those previously studied for systolic arrays.

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